FD.io VPP  v20.09-64-g4f7b92f0a
Vector Packet Processing
rdma_mlx5dv.h
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1 /*
2  *------------------------------------------------------------------
3  * Copyright (c) 2020 Cisco and/or its affiliates.
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at:
7  *
8  * http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  *------------------------------------------------------------------
16  */
17 
18 #ifndef _RDMA_MLX5DV_H_
19 #define _RDMA_MLX5DV_H_
20 
21 #undef always_inline
22 #include <infiniband/mlx5dv.h>
23 #define always_inline static_always_inline
24 
25 /* CQE flags - bits 16-31 of qword at offset 0x1c */
26 #define CQE_FLAG_L4_OK 10
27 #define CQE_FLAG_L3_OK 9
28 #define CQE_FLAG_L2_OK 8
29 #define CQE_FLAG_IP_FRAG 7
30 #define CQE_FLAG_L4_HDR_TYPE(f) (((f) >> 4) & 7)
31 #define CQE_FLAG_L3_HDR_TYPE_SHIFT (2)
32 #define CQE_FLAG_L3_HDR_TYPE_MASK (3 << CQE_FLAG_L3_HDR_TYPE_SHIFT)
33 #define CQE_FLAG_L3_HDR_TYPE(f) (((f) & CQE_FLAG_L3_HDR_TYPE_MASK) >> CQE_FLAG_L3_HDR_TYPE_SHIFT)
34 #define CQE_FLAG_L3_HDR_TYPE_IP4 1
35 #define CQE_FLAG_L3_HDR_TYPE_IP6 2
36 #define CQE_FLAG_IP_EXT_OPTS 1
37 
38 typedef struct
39 {
40  struct
41  {
42  u8 pad1[28];
44  u8 pad2[14];
45  union
46  {
49  };
50  u8 pad3[15];
52  };
53 } mlx5dv_cqe_t;
54 
56 
57 typedef struct
58 {
59  union
60  {
63  };
66 
67 typedef struct
68 {
71 } mlx5dv_rwq_t;
72 
73 #define foreach_cqe_rx_field \
74  _(0x1c, 26, 26, l4_ok) \
75  _(0x1c, 25, 25, l3_ok) \
76  _(0x1c, 24, 24, l2_ok) \
77  _(0x1c, 23, 23, ip_frag) \
78  _(0x1c, 22, 20, l4_hdr_type) \
79  _(0x1c, 19, 18, l3_hdr_type) \
80  _(0x1c, 17, 17, ip_ext_opts) \
81  _(0x1c, 16, 16, cv) \
82  _(0x2c, 31, 0, byte_cnt) \
83  _(0x30, 63, 0, timestamp) \
84  _(0x38, 31, 24, rx_drop_counter) \
85  _(0x38, 23, 0, flow_tag) \
86  _(0x3c, 31, 16, wqe_counter) \
87  _(0x3c, 15, 8, signature) \
88  _(0x3c, 7, 4, opcode) \
89  _(0x3c, 3, 2, cqe_format) \
90  _(0x3c, 1, 1, sc) \
91  _(0x3c, 0, 0, owner)
92 
93 
94 /* inline functions */
95 
96 static inline u32
97 mlx5_get_u32 (void *start, int offset)
98 {
99  return clib_net_to_host_u32 (*(u32 *) (((u8 *) start) + offset));
100 }
101 
102 static inline u64
103 mlx5_get_u64 (void *start, int offset)
104 {
105  return clib_net_to_host_u64 (*(u64 *) (((u8 *) start) + offset));
106 }
107 
108 static inline void
109 mlx5_set_u32 (void *start, int offset, u32 value)
110 {
111  (*(u32 *) (((u8 *) start) + offset)) = clib_host_to_net_u32 (value);
112 }
113 
114 static inline void
115 mlx5_set_u64 (void *start, int offset, u64 value)
116 {
117  (*(u64 *) (((u8 *) start) + offset)) = clib_host_to_net_u64 (value);
118 }
119 
120 static inline void
121 mlx5_set_bits (void *start, int offset, int first, int last, u32 value)
122 {
123  u32 mask = (1 << (first - last + 1)) - 1;
124  u32 old = mlx5_get_u32 (start, offset);
125  if ((last == 0) && (first == 31))
126  {
127  mlx5_set_u32 (start, offset, value);
128  return;
129  }
130  ASSERT (value == (value & mask));
131  value &= mask;
132  old &= ~(mask << last);
133  mlx5_set_u32 (start, offset, old | value << last);
134 }
135 
136 static inline u32
137 mlx5_get_bits (void *start, int offset, int first, int last)
138 {
139  u32 value = mlx5_get_u32 (start, offset);
140  if ((last == 0) && (first == 31))
141  return value;
142  value >>= last;
143  value &= (1 << (first - last + 1)) - 1;
144  return value;
145 }
146 
147 
148 #endif /* RDMA_MLX5DV_H */
149 
150 /*
151  * fd.io coding-style-patch-verification: ON
152  *
153  * Local Variables:
154  * eval: (c-set-style "gnu")
155  * End:
156  */
u32 mini_cqe_num
Definition: rdma_mlx5dv.h:48
u64 dsz_and_lkey
Definition: rdma_mlx5dv.h:69
unsigned long u64
Definition: types.h:89
u8 opcode_cqefmt_se_owner
Definition: rdma_mlx5dv.h:51
static heap_elt_t * last(heap_header_t *h)
Definition: heap.c:53
u16 mask
Definition: flow_types.api:52
static u64 mlx5_get_u64(void *start, int offset)
Definition: rdma_mlx5dv.h:103
unsigned char u8
Definition: types.h:56
unsigned int u32
Definition: types.h:88
static heap_elt_t * first(heap_header_t *h)
Definition: heap.c:59
unsigned short u16
Definition: types.h:57
u8 value
Definition: qos.api:54
#define ASSERT(truth)
STATIC_ASSERT_SIZEOF(mlx5dv_cqe_t, 64)
template key/value backing page structure
Definition: bihash_doc.h:44
static u32 mlx5_get_u32(void *start, int offset)
Definition: rdma_mlx5dv.h:97
struct clib_bihash_value offset
template key/value backing page structure
static void mlx5_set_bits(void *start, int offset, int first, int last, u32 value)
Definition: rdma_mlx5dv.h:121
static void mlx5_set_u64(void *start, int offset, u64 value)
Definition: rdma_mlx5dv.h:115
static u32 mlx5_get_bits(void *start, int offset, int first, int last)
Definition: rdma_mlx5dv.h:137
static void mlx5_set_u32(void *start, int offset, u32 value)
Definition: rdma_mlx5dv.h:109