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#define | INTERNAL_SS 1 |
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#define | SSE2_QOS_DEBUG_ERROR(msg, args...) fformat(stderr, msg "\n", ##args); |
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#define | SSE2_QOS_DEBUG_INFO(msg, args...) fformat(stderr, msg "\n", ##args); |
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#define | SSE2_QOS_TR_ERR(TpParms...) |
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#define | SSE2_QOS_TR_INFO(TpParms...) |
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#define | MIN(x, y) (((x)<(y))?(x):(y)) |
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#define | MAX(x, y) (((x)>(y))?(x):(y)) |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_M40AH_OFFSET 0 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_M40AH_MASK 8 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_M40AH_SHIFT 24 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_TYPE_OFFSET 2 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_TYPE_MASK 2 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_TYPE_SHIFT 10 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_CMD_OFFSET 3 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_CMD_MASK 2 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_CMD_SHIFT 0 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_M40AL_OFFSET 4 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_M40AL_MASK 32 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_M40AL_SHIFT 0 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_RFC_OFFSET 8 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_RFC_MASK 2 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_RFC_SHIFT 30 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_AN_OFFSET 8 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_AN_MASK 1 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_AN_SHIFT 29 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_REXP_OFFSET 8 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_REXP_MASK 4 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_REXP_SHIFT 22 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_ARM_OFFSET 9 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_ARM_MASK 11 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_ARM_SHIFT 11 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_PRM_OFFSET 10 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_PRM_MASK 11 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_PRM_SHIFT 0 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_CBLE_OFFSET 12 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_CBLE_MASK 5 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_CBLE_SHIFT 27 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_CBLM_OFFSET 12 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_CBLM_MASK 7 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_CBLM_SHIFT 20 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_EBLE_OFFSET 13 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_EBLE_MASK 5 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_EBLE_SHIFT 15 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_EBLM_OFFSET 14 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_EBLM_MASK 7 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_EBLM_SHIFT 8 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_CB_OFFSET 16 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_CB_MASK 31 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_CB_SHIFT 0 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_EB_OFFSET 20 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_EB_MASK 31 |
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#define | IPE_POLICER_FULL_WRITE_REQUEST_EB_SHIFT 0 |
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#define | IPE_RFC_RFC2697 0x00000000 |
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#define | IPE_RFC_RFC2698 0x00000001 |
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#define | IPE_RFC_RFC4115 0x00000002 |
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#define | IPE_RFC_MEF5CF1 0x00000003 |
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#define | SSE2_QOS_POLICER_FIXED_PKT_SIZE 256 |
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#define | SSE2_QOS_POL_TICKS_PER_SEC 1000LL /* 1 tick = 1 ms */ |
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#define | SSE2_QOS_POL_DEF_BURST_BYTE 100 |
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#define | SSE2_QOS_POL_MIN_BURST_BYTE 9*1024 |
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#define | SSE2_QOS_POL_ALLOW_NEGATIVE 1 |
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#define | SSE2_QOS_POL_COMM_BKT_MAX (1<<IPE_POLICER_FULL_WRITE_REQUEST_CB_MASK) |
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#define | SSE2_QOS_POL_EXTD_BKT_MAX (1<<IPE_POLICER_FULL_WRITE_REQUEST_EB_MASK) |
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#define | SSE2_QOS_POL_RATE_EXP_SIZE (IPE_POLICER_FULL_WRITE_REQUEST_REXP_MASK) |
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#define | SSE2_QOS_POL_RATE_EXP_MAX ((1<<SSE2_QOS_POL_RATE_EXP_SIZE) - 1) |
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#define | SSE2_QOS_POL_AVG_RATE_MANT_SIZE (IPE_POLICER_FULL_WRITE_REQUEST_ARM_MASK) |
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#define | SSE2_QOS_POL_AVG_RATE_MANT_MAX ((1<< SSE2_QOS_POL_AVG_RATE_MANT_SIZE) - 1) |
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#define | SSE2_QOS_POL_AVG_RATE_MAX |
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#define | SSE2_QOS_POL_PEAK_RATE_MANT_SIZE (IPE_POLICER_FULL_WRITE_REQUEST_PRM_MASK) |
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#define | SSE2_QOS_POL_PEAK_RATE_MANT_MAX ((1<<SSE2_QOS_POL_PEAK_RATE_MANT_SIZE) - 1) |
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#define | SSE2_QOS_POL_PEAK_RATE_MAX |
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#define | SSE2_QOS_POL_COMM_BKT_LIMIT_MANT_SIZE (IPE_POLICER_FULL_WRITE_REQUEST_CBLM_MASK) |
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#define | SSE2_QOS_POL_COMM_BKT_LIMIT_MANT_MAX ((1<<SSE2_QOS_POL_COMM_BKT_LIMIT_MANT_SIZE) - 1) |
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#define | SSE2_QOS_POL_COMM_BKT_LIMIT_EXP_SIZE (IPE_POLICER_FULL_WRITE_REQUEST_CBLE_MASK) |
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#define | SSE2_QOS_POL_COMM_BKT_LIMIT_EXP_MAX ((1<<SSE2_QOS_POL_COMM_BKT_LIMIT_EXP_SIZE) - 1) |
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#define | SSE2_QOS_POL_COMM_BKT_LIMIT_MAX |
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#define | SSE2_QOS_POL_EXTD_BKT_LIMIT_MANT_SIZE (IPE_POLICER_FULL_WRITE_REQUEST_EBLM_MASK) |
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#define | SSE2_QOS_POL_EXTD_BKT_LIMIT_MANT_MAX ((1<<SSE2_QOS_POL_EXTD_BKT_LIMIT_MANT_SIZE) - 1) |
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#define | SSE2_QOS_POL_EXTD_BKT_LIMIT_EXP_SIZE (IPE_POLICER_FULL_WRITE_REQUEST_EBLE_MASK) |
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#define | SSE2_QOS_POL_EXTD_BKT_LIMIT_EXP_MAX ((1<<SSE2_QOS_POL_EXTD_BKT_LIMIT_EXP_SIZE) - 1) |
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#define | SSE2_QOS_POL_EXT_BKT_LIMIT_MAX |
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#define | RATE256 (256114688000LL / 8LL / SSE2_QOS_POL_TICKS_PER_SEC) |
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#define | RATE128 (128057344000LL / 8LL / SSE2_QOS_POL_TICKS_PER_SEC) |
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#define | RATE64 ( 64028672000LL / 8LL / SSE2_QOS_POL_TICKS_PER_SEC) |
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#define | RATE_OVER256_UNIT 8LL |
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#define | RATE_128TO256_UNIT 4LL |
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#define | RATE_64TO128_UNIT 2LL |
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#define | MAX_RATE_SHIFT 10 |
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