2.5.1. L2 Ethernet Switching

Following sections include Throughput Speedup Analysis for VPP multi- core multi-thread configurations with no Hyper-Threading, specifically for tested 2t2c (2threads, 2cores) and 4t4c scenarios. 1t1c throughput results are used as a reference for reported speedup ratio. Input data used for the graphs comes from Phy-to-Phy 64B performance tests with VPP L2 Ethernet switching, including NDR throughput (zero packet loss) and PDR throughput (<0.5% packet loss).

2.5.1.1. NDR Throughput

VPP NDR 64B packet throughput speedup ratio is presented in the graphs below for 10ge2p1x520 and 40ge2p1xl710 network interface cards.

2.5.1.1.1. NIC 10ge2p1x520

Figure 1. Throughput Speedup Analysis - Multi-Core Speedup Ratio - Normalized NDR Throughput for Phy-to-Phy L2 Ethernet Switching.

CSIT source code for the test cases used for above plots can be found in CSIT git repository.

2.5.1.1.2. NIC 40ge2p1xl710

Figure 2. Throughput Speedup Analysis - Multi-Core Speedup Ratio - Normalized NDR Throughput for Phy-to-Phy L2 Ethernet Switching.

CSIT source code for the test cases used for above plots can be found in CSIT git repository.

2.5.1.2. PDR Throughput

VPP PDR 64B packet throughput speedup ratio is presented in the graphs below for 10ge2p1x520 and 40ge2p1xl710 network interface cards. PDR measured for 0.5% packet loss ratio.

2.5.1.2.1. NIC 10ge2p1x520

Figure 3. Throughput Speedup Analysis - Multi-Core Speedup Ratio - Normalized PDR Throughput for Phy-to-Phy L2 Ethernet Switching.

CSIT source code for the test cases used for above plots can be found in CSIT git repository.